Synthesis and Designing of Reversible Adder/Subtracter Circuits

Reversible logic circuits have emerged as a promising technology having its applications in low power CMOS, Quantum Computing, nanotechnology, and optical computing. Power is the major constraint for any circuit Each circuit demands not only low power, but fast speed. This paper is focused on the efficient design of the full Adder/Subtractor with the help of half adder subtractor with single control line The proposed design offers the efficient Adder/Subtractor in terms of gate count, garbage outputs, constant inputs and Quantum Cost. A new reversible gate COG gate is used for designing of Full adder /Subtractor. The proposed circuits will simulate in Xilinx8.2i and by writing the Code in VHDL HDL.